A typical semiconductor device such as flash memory employs STI (Shallow Trench Isolation) for element isolation to achieve increased integration. STI comprises elongate trenches formed on the semiconductor substrate which are filled with insulating films to define an isolated active region encompassed by the trenches.
JP 2006-156471 A describes STI employing two layers of insulating films for filling the element isolation trenches, where the first layer comprises a silicon oxide film comprising spin-coated polysilazane film and the second layer comprises silicon oxide film formed by HDP-CVD (High Density Plasma Chemical Vapor Deposition).
During the process of thermally treating the spin-coated polysilazane film to form the silicon oxide film, shrinking of polysilazane causes strains at the interface of polysilazane and semiconductor substrate. The semiconductor substrate suffers greater stress at portions where greater amount of polysilazane is coated; hence, strains of greater magnitude occur at such portions.
Such problem is typically observed, for instance, in peripheral circuit transistors in which the active region is surrounded by STI, and the active region is exposed to increasing amount of polysilazane. Greater stress is produced especially at the interface of the active region and the polysilazane film, providing grounds for occurrence of crystal defects and dislocation. This area is subject to even greater stress when forming a high-concentration impurity region employing LDD (Low-concentration Drain), leading to increasing possibility of dislocation.
More specifically, when forming a high-concentration impurity region taking an LDD structure in the semiconductor substrate, increased instances of crystal defects are observed at the depth of pn junction formed by ion implantation, in other words, at the depth where the impurity concentration is at its peak. Then, thermal treatment is performed to reduce crystal defects and to activate the impurity ions. The thermal treatment produces stress at the STI, more specifically at the interface of polysilazane and the active region. Thus the semiconductor substrate being subject to the above stress is susceptible to linear defects such as dislocation especially at portions affected by crystal defects. Preventive measures have been sought to suppress dislocation for eliminating grounds for increase of leak current at pn junction.
One of such measures attempted to reduce occurrence of crystal defects in the semiconductor substrate is described in Patent Publication JP 2004-228557 A. The publication discloses the approach of suppressing the occurrence of crystal defects at the region of the semiconductor substrate where impurities are introduced by ion implantation to form the source/drain region. In order to reduce occurrence of crystal defects caused by stress originating from the element isolation region, the publication takes the approach of lowering the embedded oxide film prior to ion implantation.
According to the disclosure of the above publication, the source/drain region is formed by ion implantation after the oxide film embedded in the STI is lowered by dry etching.
The negative side of this approach is that, when impurities are introduced into the semiconductor substrate by ion implantation after the embedded oxide film in the STI has been lowered, transfer of implanted ions occurs from the boundary of the semiconductor substrate and the STI where the embedded oxide film has been removed. This results in unwanted deformation of the source/drain region.
One solution to this problem may be to perform ion implantation prior to lowering of the embedded oxide film. However, this counterapproach also has a negative side in that the portion of the semiconductor substrate where impurities are introduced prior to etching maybe etched away along with the impurities by the subsequent etching. This again, results in unwanted deformation of the source/drain region.
The failure in forming the source/drain region in desired form critically affects formation of a high-concentration impurity region of LDD structure.